Improving reliability, performance, and energy efficiency of STT-MRAM with dynamic write latency
Halls department, Hall 2
Thursday, 29 December 2016
10:30 - 11:30
High write latency and high write energy are the major challenges in Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) design. The write operation in STT-MRAM is of stochastic nature. Therefore, it requires a very long timing margin to maintain an acceptable level of reliability and yield. Traditionally, Error Correction Codes (ECCs) are used to reduce the timing margin in STT-MRAM. However, they impose high storage and latency overheads. In this talk, I present a low-cost architecture-level technique to significantly reduce the amount of required timing margin. This technique employs a handshaking protocol between the memory and its controller to dynamically determine the write latency at run-time. The simulation infrastructure comprehensively models the combined effect of process variation and stochastic write behavior at circuit-level and abstracts it to architecture-level. The simulation results show that this technique not only considerably reduces the write error rate but also improves the overall system performance on average by 15.4% compared to existing solutions.
Ali Ahari received his B.Sc. and M.Sc. degrees in Computer Engineering from Sharif University of Technology in 2011 and 2013, respectively. He has been a research assistant at the Chair of Dependable Nanocomputing at Karlsruhe Institute of Technology and also he has collaborated with the Chair of Embedded Security at Ruhr University as a visiting scholar. Since September 2015 he works as a scientific staff at the Department of Microelectronic System Design (SIM) of the FZI Forschungszetruminformatik in Karlsruhe, Germany.